Today's engineers often design electronic systems so that they will function properly when a component from one manufacturer is replaced with a like component from another manufacturer. For example, most personal computers will function properly with a Pentium.RTM. processor from Intel or a K6.RTM. processor from Advanced Micro Devices (AMD). This interchangeability of components provides many advantages. For example, because more than one manufacturer can source a particular component, competition among manufacturers is increased, thus lowering the cost per component. Furthermore, if one manufacturer runs out of a particular component, the system manufacturer can obtain like components from another manufacturer and thus avoid a production delay. Additionally, for systems such as personal computers, such interchangeability provides greater flexibility to a customer by allowing him to select components that meet his quality, performance, and cost expectations.
To allow component interchangeability, a system designer often specifies the operating characteristics and parameters that a component must meet in order to function in a particular system. Thus, if a manufacturer wants to design a component of the system, then it must design the component to meet these system specifications.
Table 1 at the end of the specification is a section of Intel's PC-100 specification for Synchronous Dynamic Random Access Memories (SDRAMs) designed for use on Intel's computer boards. Specifically, this section specifies the acceptable ranges of the rise- and fall-time slew rates (Volts/nanosecond) into 50-ohm and 50 picofarad (pf) loads, respectively, and the push (switching current high) and pull (switching current low) drive currents for an SDRAM's data output drivers. These drivers, which are called DQ drivers, are the circuits that drive the data onto the data bus during a read cycle. Unfortunately, conventional DQ drivers often cannot meet all the requirements of the PC-100 specification.
FIG. 1 is a schematic diagram of a conventional DQ driver 10, which drives a data output terminal 11 of an SDRAM. During a read cycle, the driver 10 receives a DATA IN signal from a selected memory cell (not shown) on an input terminal 12, and receives its complement DATA IN on an input terminal 13. Thus, when DATA IN is logic 1, DATA IN is logic 0, and vice versa. A conventional voltage-boost circuit 14 controls an NMOS pull-up transistor 16 in response to DATA IN. The circuit 14 receives a boost voltage V.sub.BOOST, which is typically at least one threshold voltage of the transistor 16 above V.sub.DD. When DATA IN is logic 1, the circuit 14 applies V.sub.BOOST to the gate of the transistor 16, thus overdriving the transistor 16 so that it fully couples V.sub.DD to the output terminal 11. A conventional inverter 18, which includes a PMOS transistor 20 and an NMOS transistor 22, controls an NMOS pull-down transistor 24 in response to DATA IN. When DATA IN is logic 1, the transistor 22 deactivates the transistor 24 by pulling its gate to V.sub.SS, which is typically ground. Conversely, when DATA IN is logic 0, the transistor 20 activates the transistor 24 by pulling its gate to V.sub.DD. Because the transistor 24 often has a relatively high input capacitance, the channel-width/channel-length ratio, and thus the gain, of the transistor 20 is made relatively high. This allows the transistor 20 to source the relatively large activation current required to quickly charge the input capacitance and thus quickly turn on the transistor 24.
Unfortunately, although the DQ driver 10 meets most of the PC-100 specifications in Table 1, it may not meet all of them. In operation, the boost circuit 14 controls the pull-up transistor 16 such that the driver 10 does generate the rising slew rates within the specified ranges when a 50-ohm load and a 50 pf load are respectively connected between the output terminal 11 and V.sub.SS. The driver 10 also meets the push drive-current specification, which means that the transistor 16 sources current within the specified range when the output terminal 11 is at 1.65 V. But unfortunately, although the transistor 20 drives the transistor 24 such that driver 10 meets the pull drive-current specification, the driver 10 may not meet one of the 50-ohm and 50 pf falling slew-rate specifications as discussed below.
An embodiment of the driver 10 that meets one but misses the other falling slew-rate specification will now be discussed with reference to FIGS. 2 and 3 and Table 1. FIG. 2 is a graph showing the falling slew rate into a 50 pf load for the driver 10. Here, the gain of the transistor 20 is such that the transistor 24 generates a 50 pf falling slew rate of approximately 3.5 V/nS within the specified region 26 of between 1.2 and 1.8 V. Referring to Table 1, this 50 pf falling slew rate is within the specified range of 1.3-3.6 V/ns. FIG. 3 is a graph of the falling slew rate into a 50-ohm load for the same embodiment of the driver 10. Here, the gain of the transistor 20 is such that the transistor 24 generates a 50-ohm falling slew rate of approximately 16 V/nS within the specified region 26. Referring to Table 1, however, this 50-ohm falling slew rate is well above the maximum specified slew rate of 5 V/nS.
The problem with this embodiment of the driver 10 is that the gain of the transistor 20, which is set high enough for the driver 10 to meet the 50 pf falling slew-rate specification, causes the driver 10 to exceed the 50-ohm falling slew-rate specification. Unfortunately, reducing the gain of the transistor 20 so that the driver 10 meets the 50-ohm falling slew-rate specification causes the driver 10 to undershoot the 50 pf falling slew-rate specification.